In an integrated circuit device, it is often desired to utilize a plurality of clocking signals for various portions of the circuit. In order to maximize efficiency, it is preferred to generate all clocking signals used on the integrated circuit from a single clock input. Many circuit designs today employ a two-phase clocking scheme for clocking latches and registers. Typically the two phases consist of a master and slave which must be non-overlapping in order to avoid data run-through or other timing hazards. However, this non-overlap timing can be difficult to maintain across various processes, temperatures, voltages, and loading.
In a typical circuit for generating non-overlap clock signals shown in prior art FIG. 1, a single reference clock 100 is used to derive two non-overlapping clocks, a master 102 and a slave 104.
The non-overlap timing is usually implemented by having an analog delay path connected to reference clock 100 to delay each rising edge of master clock 102 by a delay time T1 and by having an analog delay path connected to reference clock 100 to delay each rising edge of slave clock 104 by a delay time T2.
A disadvantage of the prior art scheme is that the analog delays are very dependent on process parameters, operating temperature, and operating voltage. Thus, for parts which are produced with operating characteristics which fall in a weak corner of a process schmoo plot of frequency vs. voltage or temperature, the analog delay will increase as indicated by additional delay time T3 in prior art FIG. 2, resulting in a shorter HIGH pulse width T4 on clock signals 102 and/or 104. This can cause problems since the device in general will operate slower at weak corners and generally will require longer pulse widths to accommodate the longer delays through the various layers of logic circuitry.
Another disadvantage of this scheme is that the analog delay is very difficult to control across all process/temperature/voltage corners. So if a minimum amount of non-overlap time is required for the device to function properly, the circuit must be designed to provide enough delay to ensure this non-overlap time, even at a strong corner of the process schmoo. Then at the weak corner, the non-overlap time can become excessively large and impact the maximum operating frequency of the device, as mentioned above.
Therefore, it is an object of the present invention to provide a driver circuit which results in the output of non-overlapping clocking signals.
It is further an object of the present invention to provide a driver circuit which is process insensitive.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.